In integrated circuit processing, vertical connecting members (vias) between horizontal interconnection layers are used to improve planarity. The apertures that are formed have a high aspect ratio and are correspondingly difficult to fill without voids.
U.S. Pat. No. 5,173,442 illustrates a Damascene process that employs a two-level mask. U.S. Pat. No. 5,004,673 illustrates a Damascene process employing a mask of graded thickness at various locations.
U.S. Pat. No. 4,461,672 illustrates a Damascene process in which a sacrificial polysilicon layer is isotropically etched to produce a tapered opening, the taper being transferred to an underlying oxide layer. The art has long searched for a simple, low cost method of forming a Damascene-metal interconnect.